Shallow trench isolation structure for strained Si on SiGe

ABSTRACT

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductordevices in general. In particular, the invention relates to a shallowtrench isolation structure, and method for fabricating such a structure,for MOSFET devices processed on substrates which comprise SiGe basedmaterial layers.

BACKGROUND OF THE INVENTION

[0002] Today's integrated circuits include a vast number of devices.Smaller devices are key to enhance performance and to improvereliability. As MOSFET (Metal Oxide SemiconductorField-Effect-Transistor, a name with historic connotations meaning ingeneral an insulated gate Field-Effect-Transistor) devices are beingscaled down, however, the technology becomes more complex and changes indevice structures and new fabrication methods are needed to maintain theexpected performance enhancement from one generation of devices to thenext. In this regard the semiconductor that has progressed the farthestis the primary semiconducting material of microelectronics: silicon(Si).

[0003] There is great difficulty in maintaining performance improvementsin devices of deeply submicron generations. Several avenues are beingexplored for keeping device performance improvements on track. Amongthese is the use of tensilely strained Si as the basic semiconductingdevice material. The strained Si layer is typically formed by growing Siepitaxially over a relaxed graded SiGe (Ge stands for germanium) basedlayer as discussed in Materials Science and Engineering Reports R17, 105(1996), by P. M. Mooney, and in U.S. Pat. No. 5,659,187 to LeGoues etal. titled: “Low Defect Density/arbitrary Lattice ConstantHeteroepitaxial Layers” incorporated herein by reference. For instance,a heterostructure consisting of relaxed Si_(0.7)Ge_(0.3) capped with athin (20 nm) strained Si layer has electron and hole mobilities over 80%higher than bulk Si. The higher mobility leads to faster switchingspeed, higher “on” current, and lower power dissipation. A MOSFETfabricated in tensile strained Si exhibits higher carrier mobilitiesthan conventional MOSFET as it was shown for instance by K. Rim, et al.in “Enhanced performance in surface channel strained Si n and pMOSFETs”, Proceedings of the Twenty Sixth International Symposium onCompound Semiconductors Berlin, Germany 22-26 Aug. 1999. Fabrication ofa tensilely strained Si layer is also taught in U.S. patent applicationtitled: “Strained Si based layer made by UHV-CVD, and Devices Therein”,by J. Chu et al, filed Feb. 11, 2002, Ser. No. 10/073562, (IBM Docketno.: YOR920010573US1) incorporated herein by reference.

[0004] Innovations solving a problem, such as using SiGe as substratematerial, often lead to unexpected complications. Such an unexpecteddifficulty arises in isolating devices when the substrate contains Ge.The two main device isolation schemes currently used in VLSI CMOSfabrication, local-oxidation of silicon (LOCOS) and shallow trenchisolation (STI), both involve thermal oxidation of the substrate.However, thermal oxidation of SiGe based materials at high temperaturesresults in a high interface-state density, and defects caused by“snowplowing” of Ge. Therefore oxidation of SiGe based materials must beavoided in any isolation scheme.

[0005] A possible solution to this problem would be to implement an STIprocess without a grown oxide liner. However, the oxide liner is a veryimportant part of the isolation process. It serves to round the topcorners of the trench, preventing high-field regions from formingbetween a polysilicon over layer and the substrate. The grown oxideliner also reduces the density of interface states at the STI edges thatcan cause carrier depletion in these regions. The liner also can preventdopant diffusion into the STI trench, particularly if it is grown in thepresence of nitrogen to form an oxy-nitride layer. Finally, the linerreduces stress and prevents defect injection into the substrate uponsubsequent thermal processing. Therefore, without the grown liner oxide,an STI process would be difficult to implement in a manufacturingenvironment.

[0006] Recognizing the problem, structures and methods were invented toavoid the oxidizing of Ge. One scheme consists of: a trench etched intoa SiGe-containing substrate where the sidewalls of the trench arecovered by a Si liner; a grown or deposited SiO₂ passivation layer; andan insulating material that fills the trench, and which is also planarwith the wafer surface. The benefit of this structure is that it avoidsthermal oxidation of SiGe on the walls of an etched trench by using asilicon liner that has vastly superior passivation properties comparedto SiGe. This STI isolation scheme is described in U.S. Pat. Nos.5,266,813 and 5,308,785 to Comfort et al. both titled: “Isolationtechnique for silicon germanium devices” and both incorporated herein byreference.

[0007] However, the use of this prior art has significant drawbacks. Theisolation structure is planar with the substrate top surface, when itwould be desirable to have the insulating layer protrude above thesurface to prevent non-uniform oxidation of the exposed Si liner, and tooffset recessing of the isolation layers that can occur duringsubsequent processing. The thermal oxidation of the Si liner may beslower at the edge, possibly leading to enhanced breakdown of the gateoxide. This problem would be exacerbated if the dielectric in the trenchwere accidentally recessed, exposing the corner of the trench linerbefore growth of the gate oxide. If one tried to correct for theplanarity of the isolation structure and attempt to make it to protrudeout of the substrate top surface, then having the Si liner surroundinghigh up the protruding isolation can cause severe device problems. Theproblem is that the Si liner on the surface of the isolation structureis in a polycrystalline state, which is notoriously unsuitable for highperformance devices. In a MOSFET geometry, the polysilicon on thesurface of the protruding insolation would also extend continuously fromthe source to the drain at the edge of the device, and could causeleakage between source and drain. In this prior art there is nosuggestion how one could overcome the discussed difficulties.

SUMMARY OF THE INVENTION

[0008] In view of the discussed problems, this invention discloses astructure, and a method of fabricating the same, which serves theisolation purposes without such problems. This result is obtained byusing a key processing step, namely the selective epitaxial growth ofthe Si liner. Selective growth means that the Si deposits on the exposedcrystalline Si or SiGe surfaces, but does not deposit on any othersurface. Such selective epitaxial deposition techniques are widelypracticed in the electronics processing arts. In this manner one canform a high-quality passivation layer, thereby eliminating problemsassociated with the oxidation of SiGe, and at the same time avoidingproblems associated with an exposed polycrystalline Si layer on theprotruding isolation structure.

[0009] It is the object of the present invention to have an isolationthat structure does not lead to device leakage or gate oxide breakdown.

[0010] It is also an object of the present invention to teach a processfor forming the isolation region that eliminates the requirement forprecise planarization, and allows for flexibility in tailoring theheight of the isolation region.

[0011] It is a further object of the present invention to teach thestructure of a shallow-trench isolation with an Si liner formed byselective growth and subsequent oxidation of Si in the trench.

[0012] It is yet a further object of the present invention to teachdevices, circuits, and processors fabricated with the invented isolationscheme.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] These and other features of the present invention will becomeapparent from the accompanying detailed description and drawings,wherein:

[0014]FIG. 1 shows schematic cross sectional views of embodiments of theisolation structure;

[0015]FIG. 2 shows a schematic cross sectional view of the isolationstructure over a substrate comprising a buried insulator layer;

[0016]FIG. 3 shows a schematic cross sectional view of the of a MOSFETtransistor utilizing the isolation scheme of the invention; and

[0017]FIG. 4 depicts a process sequence for making the isolationstructure of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018]FIG. 1 shows a schematic of embodiments of the isolationstructure. FIG. 1A shows an embodiment where the Si liner does not reachup to the top of the surface of the wafer. FIG. 1B shows an embodimentwhere the Si liner does reach up to the top of the surface of the wafer.The two variations of the embodiment depends on the relative thicknessof the Si liner 40 and the isolator layer 50 grown on the Si liner. Thetwo embodiments of FIG. 1A and FIG. 1B are equally preferred andacceptable solutions to the objects of the invention. In FIG. 1A, theembodiment comprises a SiGe based layer 10. Layer 10 is on top of asupport structure 70, typically a Si wafer. The SiGe based layer iscapped by a Si layer 20, typically in a tensilely strained state. Thetop surface of the substrate 25, in this case is also the top surface 25of the tensilely strained Si layer 20. The support structure 70, theSiGe based layer 10, and the Si layer 20 together form the substrate.The substrate has a top surface 25, which in FIG. 1A and FIG. 1B is thetop surface of the Si layer 20. A trench is extending downward from thetop surface 25 penetrating into the SiGe based layer 10, and passingthrough the Si layer 20. The trench is filled with three materials: a Siliner 40, an oxide (SiO₂) or oxy-nitride insulator liner 50, and a oxidetrench filling dielectric 60. The trench filling dielectric 60 protrudesover the top 25 of the substrate. This protrusion of the trench fillingdielectric 60 is a significant aspect of the present invention. Thesidewall of the trench, which is formed inside the substrate, is coveredby the Si liner 40. The Si liner 40 covers all the surface of the SiGebased layer 10 which is on the trench sidewall. However, the Si liner 40does not reach as high as the top edge of the trench, which edge isformed where the trench intersects the substrate top surface 25. The Siliner 40 leaves uncovered a strip shaped surface 55 on the sidewall,where the strip shaped surface 55 runs along the sidewall edge. Becauseof this strip 55 the Si liner 40 only partially covers the surface ofthe Si layer 20 which is on the trench sidewall. In FIG. 1A the Si liner40 does not break out to the top surface 25 anywhere. FIG. 1B is exactlyas FIG. 1A with the exception that the Si liner 40 reaches higher thanthe substrate top surface 25. This can happen because even for the caseof selective epitaxy the thickness of the Si liner causes growth on thetrench sidewall which reaches over the top surface 25. However, the Siliner 40 is a monocrystalline material in its entirety, with nopolycrystalline material composition. Thus the problems in devicefabrication due to polycrystalline Si reaching beyond the top surface 25are avoided because now the Si liner 40 does not cause gate oxide orsource-to-drain leakage. Since the embodiments of FIG. 1A and FIG. 1Bare equally preferred and acceptable solutions to the objects of theinvention in further figures only the embodiment where the Si liner 40does not reach the top surface 25 will be shown. However, one skilled inthe art would notice that where Si liner 40 reaches above the topsurface of the substrate 25 is an equally acceptable embodiment.

[0019] The invention assures that by using a Si liner 40, Si is oxidizedand not the sidewall surface of the SiGe based layer 10, eliminating theGe “snowplowing” effect. Furthermore, the Si liner 10 is amonocrystalline material in an epitaxial relationship with the sidewall,therefore enabling a high-quality oxide and good Si/SiO₂ interfacequality to be obtained.

[0020] The SiGe based layers are known in the art and can have a widevariety of compositions. Their purpose is to strain the overlaying Silayer, while maintaining a “device quality” material for the overlayingSi layer. The fabrication of such layers is described, for instance, inU.S. patent application Ser. No. 10/073,562, “Strained Si based layermade by UHV-CVD, and Devices Therein”, by J. Chu et al, filed Feb. 11,2002, (Attorney Docket no.: YOR920010573US1). The composition of theSiGe based layer is typically SiGe, SiGeC, or even pure Ge, or amulti-layer structure consisting of one or more of the preceding list.

[0021] Dimensions of various layer thicknesses can vary significantlydepending, for instance, on the type of circuits that are involved inthe applications. Device technology with time is becoming more advancedalong the general tendency of shrinking dimensions. Dimension valuesgiven here should not be read as restrictive, as one skilled in the artwould recognize that several other dimensional variations might bepossible, all the while maintaining the scope of the present invention.The Si liner 40 in the trench is between about 1 nm and 50 nm thick; thestrained Si layer 20 forming the top surface is between about 1 nm and50 nm thick.; the SiGe based layer is between about 5 nm and 5 μmthick.; the insulator layer 50 grown on the Si liner 40 is between about1 nm and 100 nm thick; the strip shaped surface on the sidewall belowthe edge of the top surface of the substrate, left uncovered by the Siliner 40, is between about 1 nm and 50 nm wide; the trench dielectric 60protrudes above the top surface of the substrate by about between 1 nmand 500 nm; the trench itself reaches a depth relative to the topsurface of the substrate of about between 2 nm and 1 μm.

[0022]FIG. 2 shows a schematic cross sectional view of the isolationstructure over a substrate further comprising a buried insulator layer80. Here, the substrate comprises the buried insulator layer 80 betweenthe support 70, typically Si, and the Siege based layer 10. The buriedinsulator layer 80 is typically SiO₂. The isolation structure isessentially the same as on bulk of FIG. 1, except that as the result ofthe selective deposition of the Si liner 40, the Si liner 40, andtherefore the thermal SiO₂ layer 50, are not found over the buriedinsulator layer 80.

[0023]FIG. 3 shows a schematic cross sectional view of the of a MOSFETtransistor utilizing the isolation scheme of the invention. The MOSFETcomprises a gate electrode 110, separated from the strained Si layer 20by an insulating gate dielectric 120, which is typically SiO₂. On eitherside of the gate 110 the source and drain regions 130 and 140 areimplemented. In FIG. 3, as shown, it is not significant on which side ofthe gate is the source 130, and on which side is the drain 140. Theremaining Si, left over from the Si liner 40 after the thermaloxidation, is doped the same type as the source and drain regions andtherefore becomes part of the source and drain regions 130 and 140. Thiswas made possible by the fact that the Si liner 40 is a monocrystallinematerial due to its selective deposition. The entire source/drain andgate regions are surrounded by the thermally-grown SiO₂ layer 50, andthe trench filling dielectric 60. The MOSFET of FIG. 3 utilizes a buriedSiO₂ layer 80. One skilled in the art would notice that a similar deviceimplementation could utilize a bulk substrate and isolation scheme shownin FIG. 1. A plurality of MOSFET devices shown schematically on FIG. 3can form the basis of any system in need of MOSFET devices. Inparticular, for the case of digital processors such MOSFETs aretypically wired into CMOS circuits, which then can form all the variouslogic circuits needed by the processors.

[0024]FIG. 4 depicts a process sequence for making the isolationstructure of the invention. One skilled in the art would notice thatonly the salient features of the process of one embodiment are beingpresented. Many further steps, all known in the electronics processingarts, may be needed to completely fabricate the isolation structure.Thus the presented steps should not be read in a way that is in anymanner limiting.

[0025]FIG. 4A shows the starting substrate comprising a relaxed Siegebased layer 10, with a strained Si layer 20 on top of it, and having atop surface 25, same as the substrate top surface. The top surface 25 isthen overlaid with a capping dielectric layer 30, preferably siliconnitride to a thickness of between about 10 nm to 500 nm. This cappingdielectric acts as a stopping layer for subsequent planarization steps.Optionally, a thin etch protection SiO₂ layer 90 can be placedunderneath dielectric capping layer 30, to ensure that the substrate isnot etched during the removal of layer 30. Then a trench is etched, withthe trench cutting through the capping dielectric layer 30, andextending downward from the top surface of the substrate, which is thetop surface of Si layer 20. The trench next penetrates into the Siegebased layer 10. In this manner the trench has an auxiliary sidewallformed in the capping dielectric layer 30, and has a sidewall formed inthe substrate with crystalline layers 20 and 10. The trench has asidewall edge formed where the sidewall intersects the top surface oflayer 20. The result of these steps is shown in FIG. 4B. Next, as shownin FIG. 4C, a monocrystalline Si liner 40 is deposited by selectiveepitaxy over the sidewall, including a surface of the Siege based layer10 on the sidewall. The selective epitaxy leaves the auxiliary sidewallof the capping dielectric layer 30 void of the Si liner grown in thetrench. Preferred methods of depositing the single-crystal liner arerapid-thermal chemical vapor deposition and ultra-high-vacuum chemicalvapor deposition. These, and other such methods are widely practiced inthe electronics processing arts. FIG. 4D depicts the state of theprocess after an insulator 50 is grown on the Si liner 40, partiallyconsuming the Si liner 40. This consumption of the Si liner 40 isthinning the Si liner compared to as it was deposited on FIG. 4C. Asshown in FIG. 4C and the following ones the insulator layer 50 removesthe Si liner 40 in a strip shaped surface of the sidewall, where thestrip 55 shaped surface runs along the sidewall edge. Here the Si linerdoes not reach up to the to surface 25 of the strained Si layer 20. Thelayer inside the trench which intersects the top surface of thesubstrate is the grown insulator 50. The thermally grown insulator 50 istypically a silicon-oxide or oxy-nitride. As shown in FIG. 1B, it ispossible that the insulator 50 does not consume as much of the Si liner40 that the liner would be below the top surface 25. Next, as shown inFIG. 4E, a trench dielectric 60 is blanket deposited in a thickness thatthe trench dielectric 60 overfills the trench, beyond the top of thecapping dielectric layer 30. It is preferred that this trench dielectricconsists essentially of SiO₂. As shown in FIG. 4F, the next step is topolish the trench dielectric layer 60 until the capping dielectric 30and the trench dielectric 60 form one common surface. The cappingdielectric 30 acts as a stopping layer for the polishing step. FIG. 4Gshows the step where the trench dielectric 60 is selectively etched downto a protruding level which is above the top surface of the strained Silayer 20. This step is done typically by using a wet or dry selectiveetch. In this manner the trench is filled with a trench dielectric 60 toa protruding level which is above the substrate top surface. Finally asshown in FIG. 4H, the capping dielectric 30 is removed, whereby thetrench dielectric 60 remains protruding out of the trench to above thetop surface of the Si layer 20. The removal of the capping layer 30 isdone selectively with 5 respect to the underlying Si layer 20 and trenchdielectric 60. If the optional thin SiO₂ layer 90 were used in theprocess, then it is removed after the removal of the capping dielectric60. Layer 90 would serve in a protective role making sure that thestrained Si layer 20 is not etched during the removal of the cappingdielectric layer 30. With these etching steps the process is complete.The process illustrated in FIG. 4 was for an 10 embodiment with a bulksubstrate, but one skilled in the art would notice that the processwould be essentially identical for a substrate comprising a buried oxidelayer 80, as shown on FIG. 2.

[0026] Many modifications and variations of the present invention arepossible in light of the above teachings, and could be apparent forthose skilled in the art. The scope of the invention is defined by theappended claims.

We claim:
 1. A device structure, comprising: a substrate comprising aSiege based layer, said substrate having a top surface; a trenchextending downward from said top surface penetrating into said Siegebased layer, wherein said trench having a sidewall formed in saidsubstrate; a Si liner covering said sidewall, wherein said Si linercovers a surface of said Siege based layer on said sidewall, and whereinsaid Si liner is a monocrystalline material in an epitaxial relationshipwith said sidewall; an insulator layer grown on said Si liner; and atrench dielectric, said trench dielectric filling said trench andprotruding out of said trench to above said top surface.
 2. Thestructure of claim 1, wherein said substrate comprises a Si layer on topof said Siege based layer.
 3. The structure of claim 2, wherein said Silayer is between about 1nm and 50nm thick.
 4. The structure of claim 3,wherein said Si layer is tensilely strained.
 5. The structure of claim3, wherein said Siege based layer is between about 5 nm and 5 μm thick.6. The structure of claim 5, wherein said substrate comprises a buriedinsulator layer underneath said Siege based layer.
 7. The structure ofclaim 6, wherein said buried insulator layer consists essentially ofSiO₂.
 8. The structure of claim 1, wherein said Si liner is betweenabout 1 nm and 50 nm thick.
 9. The structure of claim 1, wherein saidinsulator layer grown on said Si liner consists essentially of SiO₂. 10.The structure of claim 1, wherein said insulator layer grown on said Siliner consists essentially of silicon-oxynitride.
 11. The structure ofclaim 1, wherein said insulator layer grown on said Si liner is betweenabout 1 nm and 100 nm thick.
 12. The structure of claim 1, wherein saidtrench dielectric protrudes above said top surface by between about 1 nmand 500 nm.
 13. The structure of claim 1, wherein said trench dielectricconsists essentially of SiO₂.
 14. The structure of claim 1, wherein saidtrench having a sidewall edge formed where said sidewall intersects saidtop surface, and wherein said Si liner leaves uncovered a strip shapedsurface on said sidewall, wherein said strip shaped surface runs alongsaid sidewall edge.
 15. The structure of claim 14, wherein said stripshaped surface is between about 1 nm and 50 nm wide.
 16. A plurality ofMOSFET devices fabricated on a top surface of a Substrate, wherein saidtop surface belongs to a tensilely strained Si layer, wherein said Silayer is in an epitaxial relationship with an underlying Siege basedlayer, and wherein said plurality of MOSFET devices comprise anisolation structure, said isolation structure comprising: a trenchextending downward from said top surface penetrating into said Siegebased layer, wherein said trench having a sidewall formed in saidsubstrate; a Si liner covering said sidewall, wherein said Si linercovers a surface of said Siege based layer on said sidewall, and whereinsaid Si liner is a monocrystalline material in an epitaxial relationshipwith said sidewall; an insulator layer grown on said Si liner; and atrench dielectric, said trench dielectric filling said trench andprotruding out of said trench to above said top surface.
 17. Theplurality of MOSFET devices of claim 16, wherein a portion of saidMOSFET devices are wired into CMOS circuits.
 18. The plurality of MOSFETdevices of claim 17, wherein said CMOS circuits form logic circuits fora digital processor.
 19. A method for making a device structure,comprising the steps of: taking a substrate comprising a Siege basedlayer, said substrate having a top surface; overlaying said substratewith a capping dielectric layer; etching a trench, wherein said trenchcutting through said capping dielectric layer and extending downwardfrom said top surface and penetrating into said Siege based layer, andwherein said trench having an auxiliary sidewall formed in said cappingdielectric layer and having a sidewall formed in said substrate;depositing by selective epitaxy a monocrystalline Si liner over saidsidewall including a surface of said Siege based layer on said sidewall,and leaving said auxiliary sidewall void of said Si liner.
 20. Themethod for making a device structure of claim 19, further comprising thesteps of: partially consuming said Si liner by growing an insulator onsaid Si liner; filling said trench with a trench dielectric to aprotruded level which is above said top surface; and removing saidcapping dielectric, whereby said trench dielectric is protruding out ofsaid trench to above said top surface.
 21. The method for making adevice structure of claim 20, wherein said filling step furthercomprises the steps of: blanket depositing said trench dielectric to athickness that said trench is overfilled; polishing said trenchdielectric until said capping dielectric and said trench dielectric formone common surface; and selectively etching down said trench dielectricto said protruded level which is above said top surface.
 22. The methodfor making a device structure of claim 19, wherein in said taking stepsaid substrate is comprising a Si layer on top of said Siege basedlayer.
 23. The method for making a device structure of claim 22, whereinsaid Si layer is chosen to be between about 1 nm and 50 nm thick. 24.The method for making a device structure of claim 23, wherein said Silayer is tensilely strained.
 25. The method for making a devicestructure of claim 19, wherein in said overlaying step said cappingdielectric is chosen to consist essentially of silicon-nitride.
 26. Themethod for making a device structure of claim 20, wherein in saidpartially consuming step said consuming removes said Si liner in a stripshaped surface on said sidewall, wherein said strip shaped surface runsalong a sidewall edge, wherein said trench having said sidewall edgeformed where said sidewall intersects said top surface
 27. The methodfor making a device structure of claim 20, wherein in said partiallyconsuming step said grown insulator on said Si liner is chosen toconsist essentially of SiO₂.
 28. The method for making a devicestructure of claim 19, wherein in said partially consuming step saidgrown insulator on said Si liner is chosen to consist essentially ofsilicon-oxynitride.
 29. The method for making a device structure ofclaim 20, wherein in said filling step said trench dielectric is chosento consist essentially of SiO₂.
 30. The method for making a devicestructure of claim 19, further comprising the step of: depositing anetch protection SiO₂ layer on said substrate prior to said overlayingstep.